(1) Field of the Invention
This invention relates to an integrated circuit and, more particularly, to an integrated circuit capable of verifying the operation speed of a circuit.
(2) Description of the Related Art
In recent years there have been many cases where an ordinary semiconductor integrated circuit to which a high-speed random access memory (RAM) is externally connected is used. The high-speed RAM is a RAM in which a data input-output rate is higher than the rate of an ordinary semiconductor tester, or a RAM the operation speed of which is so high that data which is outputted from the semiconductor integrated circuit and which is synchronized with a clock cannot be inputted from a semiconductor tester because of process variation.
There are various known methods for testing such a high-speed RAM (see, for example, Japanese Patent Laid-Open Publication No. 2003-4809).
FIG. 27 is a block diagram showing a conventional system for testing a semiconductor integrated circuit.
A semiconductor integrated circuit 90 includes an internal circuit 91 to be measured, storage circuits 92 and 93 connected to input and output sides, respectively, of the internal circuit 91, a buffer 94 for inputting a low-speed test pattern, a buffer 95 for outputting the low-speed test pattern, input terminals 96 of large-scale integration (LSI) where various signals are inputted from the outside, output terminals 97 where expected output values are outputted to the outside, and an oscillation circuit 98, such as a phase locked loop (PLL), for generating a high-speed clock signal by multiplying a low-speed clock signal.
In FIG. 27, the storage circuits 92 and 93 store data every clock during a test period by the operation of the oscillation circuit 98. Accordingly, the maximum number of test patterns from the start to stopping of the operation of the oscillation circuit 98 is limited by the capacity of the storage circuits 92 and 93. The number of test patterns is large, so the process “input data to storage circuit→lock up oscillation circuit→perform high-speed test→output data from storage circuit” must be repeated more than once.
FIG. 28 shows waveforms indicative of the operation of the conventional system.
When a test mode is data input, the storage circuit 92 is written at a low speed. When the test mode is lockup, the oscillation circuit 98 is made to operate, and is waited for to stabilize. When the test mode is a high-speed test, data stored in the storage circuit 92 is inputted and a high-speed test is performed with the storage circuit 93 as a destination to which data is outputted. When the test mode is data input-output, data to be used in the next test is written to the storage circuit 92 at a low speed and data stored in the storage circuit 93 is outputted to the outside at a low speed.
With such a test system, however, the following problems arise. To perform a troublesome test such as a test in which an animation is encoded or decoded, it is necessary to input about several megabytes of data to the storage circuit 92 and to output about several megabytes of data from the storage circuit 93. In this case, RAMs having very large capacity must be used as the storage circuits 92 and 93. Alternatively, a test must be performed plural times by using RAMs each having a capacity of several kilobytes to several tens of kilobytes. If a test is performed plural times, the state of the internal circuit 91 must be held while the oscillation circuit 98 is at a stop. In addition, the storage circuits 92 and 93 also store meaningless data, that is to say, write data which exists at the time of write enable not being asserted, read data which exists at the time of data not being needed by the internal circuit 91, and the like. As a result, storage capacity wasted increases and time is wasted in inputting unnecessary data and outputting and determining meaningless data. Therefore, the size of an integrated circuit chip increases and test time lengthens.